A power MOSFET typically includes a plurality of cells or sections that are operated in parallel, each of which includes a source portion on one planar surface and a drain portion on the opposite planar surface of a semiconductor wafer, and the current in each cell flows largely vertically between the two planar surfaces. Typically the source portions are individual localized regions of one conductivity type, N-type in N-type transistors, sharing a common source electrode overlying the one surface and contacting the wafer at the source portions. Typically the drain portions merge and form the bulk of the wafer and share a common drain electrode that extends over and contacts the opposite surface of the wafer. Surrounding each localized source portion is a separate ring-like region of the opposite conductivity, P-type in an N-type transistor. Intermediate between the overlying source electrode and the wafer there is positioned a common gate electrode, typically grid-like in structure for passage of portions of the source electrode through the interstices to make connection to the localized source portions. The gate electrode is insulated from the one surface of the wafer by a thin thermally grown surface oxide that serves as the gate insulator and overlies the surface portion of the separate regions of the opposite conductivity type that serves as the individual channels of the cells of the array.
In this device it is important to provide adequate clearance between cells for proper operation while maintaining close packing for high power capacity. In the prior art, the manufacture of the desired device has involved a number of masking operations for defining the desired structure of the different conductivity-type regions at the one surface and the proper location of the associated source and gate electrodes portions. As a consequence, inside each cell lateral area is consumed by a series of concentric mask lines. Moreover some of the space is used for mask alignment tolerances because of the difficulty of aligning exactly successive mask operations.